1. Field of the Invention
The present invention relates to a semiconductor memory. Specifically, the present invention relates to a semiconductor read only memory wherein information stored in memory cells are read.
2. Description of the Related Art
FIG. 5 shows a conventional semiconductor read only memory (ROM) 500. The semiconductor read only memory 500 includes a memory cell array including a plurality of memory cell transistors M1, M2, M3, . . . Mn, word lines WL1, WL2, . . . WLn, bit lines BIT11, BIT12, . . . BIT1n, and bit lines BIT21, BIT22, . . . BIT2n. (The memory cell transistor Mn and the bit lines BIT1n and BIT2n are not shown.) The plurality of memory cell transistors M1, M2, M3, . . . Mn are arranged in a matrix, and these transistors are MOS transistors. The word lines WL1, WL2, . . . WLn are connected to gate electrodes of the plurality of memory cell transistors. The bit lines BIT11 to BIT1n are connected to drain electrodes of the plurality of memory cell transistors, and the bit lines BIT21 to BIT2n are connected to source electrodes of the plurality of memory cell transistors.
The bit lines BIT11 and BIT12 are also connected to source electrodes of bit line selecting transistors Tr12 and Tr11, respectively. The bit lines BIT21 and BIT22 are also connected to drain electrodes of bit line selecting transistors Tr21 and Tr22, respectively. Gate electrodes of the bit line selecting transistors Tr11 and Tr12 are connected to bit line selecting lines BS11 and BS12, respectively. Drain electrodes of the bit line selecting transistors Tr11 and Tr12 are connected to a drain electrode of a charging transistor Tr4 for a reading operation (hereinafter, referred to as "read charging transistor Tr4"). A source electrode and a gate electrode of the read charging transistor Tr4 are connected to a power supply VDD. Gate electrodes of the bit line selecting transistors Tr21 and Tr22 are connected to bit line selecting lines BS21 and BS22, respectively. Source electrodes of the bit line selecting transistors Tr21 and Tr22 are connected to a ground GND.
Now, an operation for reading data stored in the memory cell transistor M2 of the semiconductor read only memory 500 is described.
Consider a case where data stored in the memory cell transistor M2 is "0". In order to read the data stored in the memory cell transistor M2, the bit lines BIT12 and BIT21 connected to the memory cell transistor M2 conduct a current. At this time, the bit line selecting lines BS11 and BS21 are high, whereas the bit line selecting lines BS12 to BS1n and BS22 to BS2n, except the bit line selecting lines BS11 and BS21, are low.
The selected bit line BIT12 is charged up to an intermediate potential through the read charging transistor Tr4 by the power supply VDD, whereas the selected bit line BIT21 goes to a ground level. Then, the word line WL2 connected to the memory cell transistor M2 goes high. The word line WL1 and the word lines WL3 to WLn, except the word line WL2, remain low. The selected bit lines BIT12 and BIT21 are connected to each other through the memory cell transistor M2, thereby forming a DC current route from the power supply VDD to the ground GND. The potential of the power supply VDD is resistive-divided by each of the resistances which are loads of the DC current route, resulting in the potential of an output signal line Dbit.
Next, consider a case where the data stored in the memory cell transistor M2 is "1". In this case, even if the word line WL2 goes high, the memory cell transistor M2 does not conduct a current. Therefore, the DC current route is not formed, and the output signal line Dbit is maintained at the intermediate potential. A sense amplifier (not shown) is capable of reading data stored in a memory cell from the change of level of the output signal line Dbit caused by the difference in data between memory cell transistors.
In the semiconductor read only memory 500 shown in FIG. 5, a sense amplifier senses a voltage drop which has been caused by a current flowing in a memory cell transistor selected by a bit line and a word line. In FIG. 5, a transition of the word line WL2 to a high level selects the memory cell transistor M2. At this time, the memory cell transistors M1 and M3 adjacent to the memory cell transistor M2 are also selected. Therefore, the bit line BIT21 connected to the memory cell transistor M1 is connected to the bit line BIT11 through the memory cell transistor M1. Since the bit line BIT11 contains a charge remaining from the previous read operation, a current flows to the bit line BIT21 through the memory cell transistor M1. This varies the value of the currents flowing through the bit lines BIT21 and BIT12.
Thus, the semiconductor read only memory 500 has difficulty in correctly reading data stored in a memory cell transistor.
Furthermore, since the semiconductor read only memory 500 is required to keep currents flowing through bit lines during a reading operation, the power consumption is increased. In order to address such a problem, for example, Japanese Laid-Open Publication No. 9-231783 discloses a method for correctly reading data by measuring the potential of a bit line which is less susceptible to a leakage current.
FIG. 6 shows an NOR type semiconductor storage device 600 wherein the potential of a bit line which is less susceptible to a leakage current is measured.
In the NOR type semiconductor storage device 600, a plurality of memory cells are connected to a word line WLn. Therefore, when a word line WL2 goes high, memory cell transistors M1, M2, and M3 connected to the word line WL2 are turned ON. As a result, a bit line current Ibit1 is divided into, for example, three currents routed through route 1, route 2 and route 3.
When leakage currents flowing through route 2 and route 3 occur, the value of bit line current Ibit1 varies. However, since the resistance between the source electrode and the drain electrode of the memory cell transistors M2 is larger relative to the off resistances of the bit line selecting transistors Tr11 and Tr12, a variation of a bit line current Ibit2 flowing through a bit line BIT21 is smaller than a variation of a bit line current Ibit1 flowing through a bit line BIT12.
In the semiconductor read only memory 500 shown in FIG. 5, the potential of the output signal line Dbit is affected by the variation of the bit line current Ibit1. Accordingly, it is difficult to correctly read information stored in the memory cell transistors. In the NOR type semiconductor read only memory 600 shown in
FIG. 6, information stored in the memory cell transistors are read by using the bit line current Ibit2 flowing through the bit line BIT21, whose variation is less than that of the bit line current Ibit1 flowing through the bit line BIT12. Specifically, the information stored in the memory cell transistors can be read correctly from the potential of the output signal line Dbit which is caused by a leakage section connected to the bit line BIT21 through a column selecting section. However, since the bit line current is kept flowing through the leakage section, the power consumption is large.
Furthermore, in the NOR type semiconductor read only memory 600 shown in FIG. 6, the resistance of the leakage section is set to a large value in order to improve the accuracy of a reading operation. Such a large resistance value of the leakage section increases a change of the potential of a bit line to be read, thereby improving the accuracy of a reading operation. However, as the resistance value increases, the reading rate decreases accordingly.